The present invention relates to semiconductor memory devices and, more particularly, to a DRAM-type semiconductor memory device using a relatively low-speed clock frequency and capable of latching a row address and a column address with one clock signal and performing a page operation.
First, a dynamic RAM (DRAM) device as a conventional semiconductor memory device will be described with reference to the drawings.
FIGS. 5(a) and 5(b) are timing charts for the data I/O of the conventional DRAM, of which FIG. 5(a) shows a read operation and FIG. 5(b) shows a write operation. In a read operation, as shown in FIG. 5(a), a row address strobe (/RAS) signal, which is a first clock signal, is initially caused to fall to activate a row-related circuit that has been in a precharged state so far, whereby a memory operation is initiated and the row address is latched. After a lapse of a given time, a column address strobe (/CAS) signal, which is a second clock signal, is subsequently caused to fall, whereby a read operation is initiated and a column address is latched. This activates memory cells connected to a selected word line as well as a sense amplifier circuit connected to a selected pair of bit lines. At this time, a write control signal /WE is brought to the HIGH level to disable a write operation, whereby a potential difference read onto the pair of bit lines connected to a selected memory cell is amplified to determine valid data and further output to the outside via a read amplifier or the like.
In a write operation also, as shown in FIG. 5(b), the /RAS signal is initially caused to fall to latch a row address and then the /CAS signal is caused to fall to latch a column address. This activates the memory cell connected to the selected word line as well as a sense amplifier connected to the selected pair of bit lines. At this time, the write control signal /WE is shifted the LOW level to enable a write operation and valid data to be held in the selected memory cell is input from a write amplifier or the like.
In the present embodiment, the mark / preceding the name of a signal indicates that the signal is inverted. The signal preceded by the mark / is in the active state when it is LOW (active LOW).
However, the conventional DRAM device requires two clock signals for synchronization to latch a row address and a column address for selecting one from a plurality of memory cells in a memory cell array, which are the RAS signal and the CAS signal. Accordingly, control operation over the clockbecomes complicated. In the case of merging the DRAM and a logic circuit into one chip, designing difficulties are particularly increased.